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MIPI

High-speed low-power Serial Link
The future mobile serial link standard has been defined by the Mobile Industry Processor Interface alliance, and is defined as a multi-Gb/s low power differential link. There are two popular standards for the physical layers for these standards: D-PHY and M-PHY. The D-PHY is a mixed-signal core that can be used for both DSI-1 (Display Serial Interface) and CSI-2 (Camera Serial Interface), while different digital controllers are necessary for each of these standards. DSI and CSI are the most popular MIPI-based standards today. Next-generation devices are expected to witness large amounts of data being transferred across the chip-to-chip and chip-to-peripheral interfaces and the MIPI alliance is specifying these interface through a set of new high-speed standards: DigRFv4 (data interface between the RFIC and the BBIC), CSI-3 (data interface between the camera and the application processor), DSI-2 (data interface between the display and the application processor) and UniPro (Unified Protocol that will form the basis for CSI-3, DSI-2 and the Universal Flash Storage (UFS)). All these standards use the MPHY as the physical layer for the interface. The MIPI body is extremely well represented by the industry and has got wide-spread acceptance. It is our firm belief that MIPI will be the standard of the future for mobile chips. Cosmic Circuits is a contributing member of the MIPI Alliance, and will continue to be involved in the specification effort.

Advantages of the MIPI interface
The MIPI interface has been specified to specifically address

  1. It is low-power, increasing battery life
  2. It is scalable – allows for additional data-lanes - can double or triple data-rates.
  3. Supports bi-directional transfer
  4. Can be implemented in nanometer CMOS technologies
  5. Uses low-voltage power-supplies – appropriate for a mobile environment
  6. Different speed modes with different power levels allows flexibility depending on use-situation   

Cosmic Circuits DPHY/MPHY
Cosmic Circuits provides silicon proven solutions for both DPHY and MPHY with a roadmap that extends into the advanced deep submicron nodes. These solutions achieve best-in-class area and power and the IP is modular keeping in mind the it’s anticipated wide-spread usage and the need for multiple configurations. Cosmic Circuits offers both universal MPHY cores that can support the entire range of applications and ultra low-area/power DigRFv4 optimized cores specifically targeting the DigRFv4 standard. Reference boards for DPHY and MPHY are available to select customers on request.
 

The IP supports the specifications described in v0.9 of the D-PHY spec. The digital D-PHY is integrated, and interfaces with the controller. The architecture supports connection of multiple data lanes in parallel – up to 4 data lanes can be connected to increase the total through-put. Customizable to user determined configurations, pairing with Cosmic Circuits MIPI® and low-jitter PLL. The foot-print is rectangular for any configuration.

  • Supports MIPI® v1.0 Specifications
  • 1Gbps data transfer rate per lane
  • HS, LP and ULPS modes supported
  • Digital D-PHY integrated for interface to PPI
  • LP-TX and LP-RX for bi-directional transmission in LP mode
  • Dynamic impedance control for LP-TX
  • HS and LP modes automatically
  • Expandable to support 4 data lanes
  • Built-in contention detection
  • Automatic termination controls

Design Architecture

OVERALL DESIGN
  1. Designed by analog engineers with broad and deep analog expertise
  2. Based on thorough understanding of factors that limit the performance
  3. Optimal choice of design parameters achieved including random mismatch on silicon
  4. Analog implementation uses an intelligent mix of core & IO transistors
  5. 1.2V design for low-power and area

CABLE MODELING
  1. Accurate Cable modeling with S-parameters
  2. “Real-World” simulations that model end-to-end parasitics
  3. Flex cable modeling to account for data-clock coupling

TRANSMIT
  1. Fast-transient amplifier based transmit
  2. Pre-compensating load scheme used
  3. Uses a smart dynamic impedance scheme to achieve slew-rate compliance

RECEIVE
  1. Receive pre-amp designed for low-power
  2. LDO regulator to reduce power-supply effects and improve BER

 

The Cosmic D-PHY Advantage

  • Fully featured and compliant to V1.0
  • Reliability - wide eye-opening across process corners
  • Performance – 1Gbps per lane
  • Optimal solution – low-power and compact foot-print
  • Modular and Scalable solution – multiple lanes
  • Built-in voltage regulator reduces external BOM cost
  • 4-level metal solution allows higher level metal for power

Modular approach



Silicon that performs



The silicon characterization includes injecting noise onto the power supply to evaluate the performance close to and harsher than the real-world effects. The MIPI transmitter and receiver are connected through a flex cable, and the digital data at the transmitted end is compared real-time with the data received. The figure shows the transition from the LP mode to the HS mode. The transmitted data cycles through the LP states prescribed in the protocol, and transitions to the HS mode where a known start-of-transmission (SOT) sequence is transmitted. The SOT sequence is followed by the high-speed data.



The following table captures the bit-error performance with injected supply noise and across power-supply voltages, with a 10” flex-cable connecting the transmitter to the receiver. Zero errors were seen over long test-times.

 

Customization and Support
We are customer-centric in our approach to support. Starting from working hand-in-hand with our customers on detailed specifications, to customizing the IP to specific application requirements, through providing a smooth integration experience (reviews and reviews), all the way through till production ramp. You get to talk directly with our R&D engineers in an easy and direct manner.



We offer to characterize your SOC silicon for the MIPI section. Our well-proven silicon-characterization methodology based on an UI is put to use to cut your time-to-market.

For CMOS imaging:
Cosmic's experience with CMOS Imaging process nodes enables us to quickly offer our MIPI cores in your CMOS-Image-Sensor process node.

For Application Processors:
With silicon-proven 80nm and 65nm cores and a roadmap for 40nm, coupled with quick customization & process porting to the required technology node, Cosmic is in a position to effectively address your MIPI mixed-signal requirements in nanometer process nodes.

 

Customer Speak:
Dr. Moon Kabju, Director of R&D Division, MTekVision
"Our mobile application processor SOCs and the market we serve requires differentiation in terms of low-power and low cost. Integrating a MIPI interface reduces system power and allows for easier interoperability. But we needed a mixed-signal partner that could deliver with certainty. Cosmic brought good technology and a supportive team that we could rely on. We are happy that their IP integrated into our chip has worked first pass and being taken to mass production in TSMC. Overall, MTek's experience with Cosmic has been smooth and rewarding"

 
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