The physical layer for these standards is defined as a multi-Gb/s low-power differential link. While the D-PHY supports data rates up to 1Gb/s (with increased speed support by employing a multi-lane approach), a more recent standard for the PHY called the MPHY supports data rates up to 5Gb/s per sub-link. Moreover, MPHY does not need a separate clock lane (the clock is embedded in the data) and is defined to consume very low power/Mbps of throughput. The CSI and DSI standards are today driving increasing adoption of D-PHY, while specific emerging applications needing higher throughput are getting designed with the MPHY. Such an approach also makes sure that the complexity and die-size are appropriate to the application. Kindly scroll below to view our MIPI solutions.